ics525-07/08 mds 525-07/08 b 1 revision 031706 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com lvcmos user configurable clock preliminary information description the ics525-07/08 are the most flexible way to generate a high-quality clock output from an inexpensive crystal or clock input at low supply voltages. the user can configure the device to produce nearly any output frequency from any input frequency by grounding or floating the select pins or by driving or hard wiring the select pins high or low. neither microcontroller, software, nor device programmer are needed to set the frequency. using phase-locked loop (pll) techniques, the device accepts a standard fundamental mode, inexpensive crystal to produce output clocks up to 250 mhz. it can also produce a highly accurate output clock from a given input clock, keeping them frequency locked. for similar capability with a serial interface, use the ics307. this product is intended for clock generation. it has low output jitter (variation in the output period), but input to output skew is not defined nor guaranteed. features ? packaged as 28-pin ssop (150 mil body) ? available in pb (lead) free package, rohs 5/6 compliant ? user determines the output frequency by setting all internal dividers ? eliminates need for custom oscillators ? low voltage operation ? pull-ups on all select inputs ? input crystal frequency of 5 - 27 mhz ? input clock frequency of 2 - 50 mhz ? compensated loop bandwidth ? enhanced low frequency operation (-08 version) ? low jitter ? duty cycle of 45/55 up to 250 mhz ? operating voltage of 1.8 v to 2.5 v ? ideal for oscillator replacement ? available in commercial and industrial temperature ranges block diagram vdd gnd 2 2 clk ref reference divider phase comparator, charge pump, and loop filter vco vco divider output divider r configuration pins v configuration pins s configuration pins x1/iclk x2 crystal or clock input optional crystal capacitors crystal oscillator pd vdd gnd 2 2 clk ref reference divider phase comparator, charge pump, and loop filter vco vco divider output divider r configuration pins v configuration pins s configuration pins x1/iclk x2 crystal or clock input optional crystal capacitors crystal oscillator pd
lvcmos user configurable clock mds 525-07/08 b 2 revision 031706 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-07/08 preliminary information pin assignment (ics525-07) pin descriptions (ics525-07) key: i(pu) = input with internal pull-up resistor; x1, x2 = crystal connections 18 7 17 8 16 9 15 x1/iclk 10 x2 11 gnd 12 clk 13 v0 14 v1 gnd pd v8 v2 v7 v5 v3 v6 22 21 20 19 v4 ref 5 6 s2 vdd vdd 24 23 r0 3 4 s0 s1 r1 26 25 r2 1 2 r5 r6 r3 28 27 r4 pin number pin name pin type pin description 1, 2, 24-28 r5, r6, r0-r4 i(pu) reference divider word input pins. 3, 4, 5 s0, s1, s2 i(pu) select pins fo r output divider. see table on page 4. 6, 23 vdd power connect to vdd. 7 x1/iclk x1 crystal connection. connect to a parallel resonant fundamental crystal or input clock. 8 x2 x2 crystal connection. connect to a crystal or leave unconnected for clock. 9, 20 gnd power connect to ground. 10 - 18 v0 - v8 i(pu) vco divider word input pins. 19 pd input power-down. active low. turns off en tire chip when low. clock outputs stop low. 21 clk output pll output clock. 22 ref output reference output. buffered crystal oscillator (or clock) output.
lvcmos user configurable clock mds 525-07/08 b 3 revision 031706 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-07/08 preliminary information pin assignment (ics525-08) pin descriptions (ics525-08) 18 7 17 8 16 9 15 x1/iclk 10 x2 11 gnd 12 clk 13 v0 14 v1 gnd pd v8 v2 v7 v5 v3 v6 22 21 20 19 v4 ref 5 6 s2 vdd vdd 24 23 r0 3 4 s0 s1 r1 26 25 r2 1 2 r5 s3 r3 28 27 r4 pin number pin name pin type pin description 1, 24-28 r5, r0-r4 i(pu) reference divider word input pins. 2, 3, 4, 5 s0, s1, s2, s3 i(pu) select pins for output divider. see table on page 4. 6, 23 vdd power connect to vdd. 7 x1/iclk x1 crystal connection. connect to a parallel resonant fundamental crystal or input clock. 8 x2 x2 crystal connection. connect to a crystal or leave unconnected for clock. 9, 20 gnd power connect to ground. 10 - 18 v0 - v8 i(pu) vco divider word input pins. 19 pd input power-down. active low. turns off en tire chip when low. clock outputs stop low. 21 clk output pll output clock. 22 ref output reference output. buffered crystal oscillator (or clock) output.
lvcmos user configurable clock mds 525-07/08 b 4 revision 031706 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-07/08 preliminary information output frequency and output divider table (ics525-07) output frequency and output divider table (ics525-08) s2 pin 5 s1 pin 4 s0 pin 3 clk output divider output frequency range (mhz) vdd = 2.5 v vdd = 1.8 v min max min max 0 0 0 12 6 20.8 6 16 0 0 1 2 37 125 37 100 010 16 5 15.63 5 12.5 0 1 1 4 20 62.5 20 50 1 0 0 5 15 50 15 40 1 0 1 7 11 35.7 11 28 1 1 0 1 75 250 75 200 1 1 1 3 25 83.33 25 66 s3 pin 2 s2 pin 5 s1 pin 4 s0 pin 3 clk output divider output frequency range (mhz) vdd = 2.5 v vdd = 1.8 v min max min max 0 0 0 0 2 75 250 75 200 0 0 0 1 3 50 167 50 133 0 0 1 0 4 38 125 38 100 0011 5 30 100 30 80 0100 7 21.4 71 21.4 57 0101 8 18.7 62 18.7 50 0110 9 16.7 55 16.7 44 0 1 1 1 10 15 50 15 40 1 0 0 0 11 13.6 45 13.6 36 1 0 0 1 13 11.5 38 11.5 30 1 0 1 0 14 10.7 35 10.7 28.5 1 0 1 1 15 10 33 10 26.6 1 1 0 0 17 8.8 29.4 8.8 23.5 1 1 0 1 19 7.9 26.3 7.9 21 1 1 1 0 48 3.0 10.4 3.0 8.3 1 1 1 1 128 1.2 3.9 1.2 3.9
lvcmos user configurable clock mds 525-07/08 b 5 revision 031706 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-07/08 preliminary information external components/crystal selection decoupling capacitors the ics525-07/08 require two 0.01f decoupling capacitors to be connected between vdd and gnd, one on each side of the chip. the capacitor must be connected close to the device to minimize lead inductance. crystal load capacitors the approximate total on-chip capacitance for a crystal is 16 pf, so a parallel resonant, fundamental mode crystal with this value of load (correlation) capacitance should be used. for crysta ls with a specified load capacitance greater than 16 pf, crystal capacitors may be connected from each of the pins x1 and x2 to ground as shown in the block diagram. the value (in pf) of these crystal caps should be (cl -16)*2, where cl is the crystal load capacitance in pf. these external capacitors are only required for applications where the exact frequency is critical. for a clock input, connect to x1 and leave x2 unconnected (no capacitors on either). configuring the frequency the ics525-07/08 output frequency is determined by its internal dividers according to this equation: v is the feedback divider and can be 8, 9, 10, 12...519 (not 11). for the ics525-07, r is the reference divider and can be 2, 3, 4...129. for the ics525-08, r can be 1, 2...64. for the ics525-07, od can be 1, 2, 3, 4, 5, 7, 12, or 16. for the ics525-08, od can be 2, 3, 4, 5, 7, 8, 9, 10, 11, 13, 14, 15, 17, 19, 48, or 128. the vco must be kept in its operating range according to this equation: ics525-07 ics525-08 the phase detector must be kept in its operating range according to this equation: optimum values for v , r , and od are found iteratively by applying the above equations. choosing a smaller value of r will give better jitter. a calculator program is available on the ics website to automate the process. after determining v , r , and od , convert them to the pin address. v8...0 = binary(v - 8) example: v = 17, v8...0 = 000001001 for the ics525-07, r6...0 = binary(r - 2) example: r = 15, r6...0 = 0001101 for the ics525-08, r5...0 - binary(r) example: r = 15, r5...0 = 001101 s2...0 or s3...0 is configured according to the tables on page 4. all of the configuration pins have on-chip pull-up resistors, so pins can be floated to generate a ?1?, or tied to ground for a ?0?. they can also be driven directly by logic signals. output termination the output driver impedance is approximately 17 ohms. use a 33 ohm series termination resistor on each output to match a 50 ohm trace. reference source the initial accuracy and te mperature stability of the output frequency is determined by the reference frequency source, the crystal, or the input clock. the pll will track the input frequen cy, so if the crystal is running at +5 ppm the clk frequency will also be +5 ppm. a low amplitude sinusoidal reference (such as the 1 v p-p signal from a tcxo) can be used by the ac coupling it to the x1 pin with a 0.1 f capacitor. the x1 pin is self-biasing. f out = v * f in r * od v * f in r 75 mhz < 200 mhz (1.8 v) 250 mhz (2.5 v) < v * f in r 150 mhz < 400 mhz (1.8 v) 500 mhz (2.5 v) < f in r 250 khz <
lvcmos user configurable clock mds 525-07/08 b 6 revision 031706 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-07/08 preliminary information absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics525-07/08. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. dc electrical characteristics unless stated otherwise, vdd = 1.8 v to 2.5 v item rating supply voltage, vdd 5 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature, commercial 0 to +70 c ambient operating temperature, industrial -40 to +85 c storage temperature -65 c to 150 c junction temperature 125 c soldering temperature 260 c (max. of 10 seconds) parameter symbol conditions min. typ. max. units operating voltage vdd 1.6 2.25 v operating supply current, 15 mhz crystal idd 60 mhz out, no load tbd ma operating supply current, power-down idd pin 19 = 0 tbd ma input high voltage v ih 0.65vdd v input low voltage v il 0.35vdd v output high voltage v oh i oh = -8 ma 0.75vdd v output low voltage v ol i ol = 8 ma 0.25vdd v short circuit current clk and ref outputs 55 ma input capacitance c in v, r, s pins and pin 19 4 pf on-chip pull-up resistor r pu v, r, s pins and pin 19 270 k ?
lvcmos user configurable clock mds 525-07/08 b 7 revision 031706 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-07/08 preliminary information ac electrical characteristics unless stated otherwise, vdd = 1.8 v to 2.5 v note 1: phase relationship between input and output can change at power-up. parameter symbol conditions min. typ. max. units input frequency f in crystal input 5 27 mhz clock input 2 50 mhz output frequency (ics525-07) f out -40 to +85 c (vdd=2.5) 5 250 mhz output frequency (ics525-08) f out -40 to +85 c (vdd=2.5) 1.2 250 mhz output clock rise time 20% to 80% (vdd=2.5) 1 ns output clock fall time 80% to 20% (vdd=2.5) 1 ns output frequency (ics525-07) f out -40 to +85 c (vdd=1.8) 5 250 mhz output frequency (ics525-08) f out -40 to +85 c (vdd=1.8) 1.2 250 mhz output clock rise time 20% to 80% (vdd=1.8) 1.5 ns output clock fall time 80% to 20% (vdd=1.8) 1.5 ns output clock duty cycle at vdd/2 45 49 to 51 55 % power-down time, pd low to clocks stopped 50 ns power-up time, pd high to clocks stable 5ms absolute clock period jitter, vdd = 2.5 v t ja deviation from mean ps one sigma clock period jitter, vdd = 2.5 v t js one sigma ps absolute clock period jitter, vdd = 1.8 v t ja deviation from mean ps one sigma clock period jitter, vdd = 1.8 v t js one sigma ps
lvcmos user configurable clock mds 525-07/08 b 8 revision 031706 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-07/08 preliminary information package outline and package dimensions (28-pin ssop, 150 mil body) package dimensions are kept current with jedec publication no. 95, mo-153 index area 1 2 28 d e1 e seating plane a 1 a a 2 e - c - b aaa c c l millimeters inches symbol min max min max a 1.351.75.053.069 a1 0.10 0.25 .0040 .010 a2 -- 1.50 -- .059 b 0.200.30.008.012 c 0.180.25.007.010 d 9.80 10.00 .386 .394 e 5.806.20.228.244 e1 3.80 4.00 .150 .157 e 0.635 basic 0.025 basic l 0.401.27.016.050 0 8 0 8 aaa -- 0.10 -- 0.004
lvcmos user configurable clock mds 525-07/08 b 9 revision 031706 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics525-07/08 preliminary information ordering information parts that are ordered with a ?lf? suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics525r-07 ics525r-07 tubes 28-pin ssop 0 to +70 c ics525r-07t ics525r-07 tape and reel 28-pin ssop 0 to +70 c ics525r-07lf ics525r-07lf tubes 28-pin ssop 0 to +70 c ics525r-07lft ics525r-07lf tape and reel 28-pin ssop 0 to +70 c ics525ri-07 ics525r-i07 tubes 28-pin ssop -40 to +85 c ics525ri-07t ics525ri-07 tape and reel 28-pin ssop -40 to +85 c ics525ri-07lf ics525ri07lf tubes 28-pin ssop -40 to +85 c ics525ri-07lft ics525ri07lf tape and reel 28-pin ssop -40 to +85 c ics525r-08 ics525r-08 tubes 28-pin ssop 0 to +70 c ics525r-08t ics525r-08 tape and reel 28-pin ssop 0 to +70 c ICS525R-08LF ICS525R-08LF tubes 28-pin ssop 0 to +70 c ICS525R-08LFt ICS525R-08LF tape and reel 28-pin ssop 0 to +70 c ics525ri-08 ics525ri-08 tubes 28-pin ssop -40 to +85 c ics525ri-08t ics525ri-08 tape and reel 28-pin ssop -40 to +85 c ics525ri-08lf ics525ri08lf tubes 28-pin ssop -40 to +85 c ics525ri-08lft ics525ri08lf tape and reel 28-pin ssop -40 to +85 c
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